1. Field of the Invention
The invention relates to telecommunications. More particularly, the invention relates to desynchronizers utilized in a high density demapper for a SONET network component.
2. State of the Art
The Synchronous Optical Network (SONET) or the Synchronous Digital Hierarchy (SDH), as it is known in Europe, is a common transport scheme which is designed to accommodate both DS-1 (T1) and E1 traffic as well as multiples (DS-3 and E-3) thereof. A DS-1 signal consists of up to twenty-four time division multiplexed DS-0 signals plus an overhead bit. Each DS-0 signal is a 64 kb/s signal and is the smallest allocation of bandwidth in the digital network, i.e. sufficient for a single telephone connection. An E1 signal consists of up to thirty-two time division multiplexed DS-0 signals with at least one of the DS-0s carrying overhead information. Developed in the early 1980s, SONET has a base (STS-1) rate of 51.84 Mbit/sec in North America. The STS-1 signal can accommodate 28 DS-1 signals or 21 E1 signals or a combination of both. In Europe, the base (STM-1) rate is 155.520 Mbit/sec, equivalent to the North American STS-3 rate (3*51.84=155.520). The STS-3 (STM-1) signals can accommodate 63 E1 signals or 84 DS-1 signals, or a combination of both. When combined in an STS-3 (STM-1) signal, the individual E1 and/or T1 signals are referred to as tributary units (TUs) or channels. The abbreviation STS stands for Synchronous Transport Signal and the abbreviation STM stands for Synchronous Transport Module. STS-n signals are also referred to as Optical Carrier (OC-n) signals when transported optically rather than electrically.
Within the synchronous optical network structure, traffic consisting of continuous signals (e.g. T1 and E1 signals) are transported between network elements by “mapping” the signals into “containers” or “tributaries” of different sizes. Payload mapping in SONET or SDH is not uniform, resulting in payload bits being assigned to complete bytes. Some of these bytes contain overhead information or reserved bits. This generates “mapping jitter”. As the payloads of the containers are passed from the originating point through network elements to the terminating point, they are remapped into other containers that may be timed by different clocks. Clock differences are compensated by the use of pointers that identify the start of the virtual container carrying a T1 or E1 signal. Periodic pointer increments and decrements indicate payload movement and result in “pointer jitter”. When the signals are eventually restored from the last container, by “demapping”, there are instantaneous periods where the restored data may burst or carry no information. This irregularity in signals is referred to generally as “jitter”. When the signal is returned to its original form, i.e. a plurality of T1/E1 signals, desynchronizers are used to create a continuous stream of bits at the average originating clock rate with little or no jitter and with no loss of data. Current desynchronizers remove mapping and pointer jitter by the use of elastic storage of information where the storage level of the elastic store device defines the output of a phase locked loop used to regenerate the average originating clock.
In a conventional demapper/desynchronizer, a separate phase locked loop and elastic storage (FIFO) is provided for each T1/E1 signal. Each phase locked loop includes circuitry for desynchronizing a T1 signal or an E1 signal, but not both. Consequently, in order to provide sufficient desynchronizers for a completely de-mapped STS-3 signal, conventional equipment provides 63 E1 desynchronizers or 84 T1 desynchronizers or a combination of both. In order to be assured of the capability of desynchronizing any combination of T1 and E1 signals, the equipment must include 63 E1 desynchronizers and 84 T1 desynchronizers. This results in a relatively large number of unused desynchronizers at any given time.
The modern practice in SONET technology is to provide switch components on chips which, when linked together, form “path”, “section”, and “line” terminating equipment. Signals are treated differently at path, section, and line terminating equipment. At line and section terminating equipment, some or all signals may be remapped without demapping or desynchronizing. At path terminating equipment all signals are demapped and desynchronized. Thus, it is desirable to provide a demapper/desynchronizer on a separate chip or set of chips because some terminating equipment will not need any demapper/desynchronizer. However, it is not practical to provide 63+84 desynchronizers on a single chip.